Superscalar-microprocessor-stimulator

superscalar out of order RISC microprocessor stimulator.

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superscalar microprocessor stimulator

Announcments

Current Deadline: 28/11 11:59 PM

Please push all commits to the dev branch, NOT the master branch. The master branch should be only left for completely stable commits, and managed via GitHub. (i.e. through pull requests) of course create a branch with your new feature first.

Description

The goal of this project is to implement an architectural simulator capable of assessing the performance of a simplified superscalar out-‐‐of-‐‐order 16-‐‐bit RISC processor that uses Tomasulo’s algorithm with speculation taking into account the effect of the cache organization.

Contribution

TODO

Getting Started

Conventions